Hot Chips puts AI racks and server CPUs on display
Summary
Hot Chips’ disclosures show AI infrastructure competition moving decisively from individual accelerators to tightly co-designed racks, CPUs, fabrics, memory hierarchies, cooling, and software. NVIDIA and AMD are optimizing AI factories around long-context, agentic workloads, while Intel, Arm, and Fujitsu are treating CPU memory bandwidth and efficiency as equally strategic parts of that stack. At the application layer, coding agents and local models are making the economics of model access, deployment, and developer productivity more visible.
Advancing price-performance for developers with GPT‑5.6 in Kiro
OpenAI has made its GPT-5.6 family—Sol, Terra, and Luna—available in AWS’s Kiro software-development agent. Kiro converts high-level intent into requirements, technical designs, and executable tasks, giving the models structured context about a team’s codebase and standards for longer-running work. OpenAI and AWS say GPT-5.6 Terra completed Terminal-Bench 2.1 tasks in Kiro at roughly 82% lower cost, attributing the result to spec-driven grounding and fewer failed iterations. The companies say they will continue optimizing the models and Kiro environment.
Read the source →llm-anthropic 0.27
Version 0.27 of Simon Willison’s Anthropic plugin for LLM is principally a compatibility update for the Anthropic Python SDK 1.0.0. That SDK moves from httpx to httpx2, mirroring a similar transport change in OpenAI’s Python library 3.0.0. Willison used Claude Code with Anthropic’s migration guide to upgrade the dependency and make the tests pass, illustrating the intended upgrade path for the plugin.
Read the source →Insane Claude Design Skills You Need To Actually Build Beautiful Sites
The video argues that stronger foundation models still tend to reproduce recognizable design patterns, so reusable design skills are useful as steering mechanisms rather than substitutes for the model. It distinguishes skills that impose lengthy workflows yet produce generic pages from a smaller set that the presenter says yields materially better results. The examples include Emil Kowalski’s nine-skill collection, whose components target separate design concerns, including an Apple-design skill that packages Apple-like product principles. The presenter says these skills can be installed in Claude settings and used across Claude Design, Claude Code, Codex, and other agents.
Read the source →AMD MI400 GPU at Hot Chips 2026
AMD presented its MI400/MI455X architecture as the accelerator inside its forthcoming 72-GPU Helios rack, targeting frontier training, fine-tuning, and persistent inference. AMD quotes 2.9 exaflops, 31 TB of HBM4, and 1.7 PB/s of HBM bandwidth per rack; each MI455X has 432 GB of HBM4 at 23.3 TB/s and 256 work-group processors. Relative to MI355X, AMD highlights larger caches and memory, up to 40.26 PFLOPS MXFP4 peak compute, dedicated data movement, and ROCm measurements such as 3.8x higher FP8 MLA decode performance. The hardware case is paired with ROCm tools and agent integrations intended to reduce the practical cost of moving workloads from CUDA.
Read the source →NVIDIA Vera Rubin NVL72 Rack at Hot Chips 2026
NVIDIA framed Vera Rubin as an AI-factory redesign for agentic inference, where long contexts, tool calls, and multi-turn work make time to first token, interruptions, and tokens per watt as important as peak FLOPS. Its NVL72 design links 72 GPUs through sixth-generation NVLink, claiming 3.6 TB/s of all-to-all bandwidth per GPU, while a 100 MW factory configuration is rated at 2 ZFLOPS NVFP4 inference, 1.4 ZFLOPS training, 11 PB of HBM4, and 800 PB/s of memory bandwidth. Rubin adds adaptive 2:4 sparsity and a sparse-attention path that NVIDIA says can accelerate downstream SoftMax and BMM2 work about 2x without model changes in most cases. The rack design also pursues warm-water cooling, 800 VDC power, cable-free fanless compute trays, and easier serviceability as system-level contributors to usable throughput.
Read the source →Waymo Sensor Fusion Processor at Hot Chips 2026
Waymo detailed a purpose-built sensor-fusion ASIC for the latency-critical path from camera, lidar, and radar inputs to embeddings in its autonomous-driving stack. The N5 chip is a 208 mm², sub-75 W package with LPDDR5X, PCIe Gen5 x8, 25G Ethernet, a custom carTPU/ISP/codec/MIPI path, and third-party GPUs for heavier sensor math. Waymo cites 160 INT8 TOPS and 80 FP16 TFLOPS, but emphasizes achieved latency and co-design over raw throughput: ahead-of-time compilation creates model-wide mega-kernels and keeps working sets in SRAM. The processor is designed for low-batch, first-pixel-to-embedding latency and is already deployed in sixth-generation Waymo vehicles, according to the presentation.
Read the source →Intel Diamond Rapids the 2027 Intel Xeon at Hot Chips 2026
Intel’s 2027 Xeon 7 Diamond Rapids uses a modular design in which compute-building-block chiplets connect to Fabric Hubs that centralize memory and I/O. A top configuration combines four compute blocks for up to 256 cores, 1.28 GB of last-level cache, 1.6 TB/s of memory bandwidth, and 128 lanes configurable for PCIe Gen6, CXL 3, or UPI 3. The 18A-P platform uses Foveros 3D direct die-to-die bonding, puts coherence filtering on die rather than in DRAM, and includes QAT, DSA, and IAA acceleration complexes. Intel is also extending x86 with spill-and-fill instructions that expose 32 integer registers while retaining source-level software compatibility after recompilation.
Read the source →Arm’s AGI Data Center CPU at Hot Chips 2026
Arm introduced AGI as its first complete commercial server CPU rather than an IP design, a shift that puts the company directly in the server-chip market. The chip uses two N3P chiplets and up to 136 active Neoverse V3 cores, with 12 DDR5 channels, over 800 GB/s of aggregate memory throughput, 96 PCIe Gen6 lanes, CXL 3.0 support, and a 300 W TDP. A UCIe die-to-die link supplies 1 TB/s in each direction so the two chiplets can approach monolithic behavior in a NUMA configuration. Arm is positioning the design for agentic-AI servers, emphasizing energy efficiency, memory bandwidth, and a roadmap of future in-house data-center SoCs.
Read the source →Fujitsu’s Arm-based Monaka Data Center CPU at Hot Chips 2026
Fujitsu’s Monaka is a 2027 Armv9.3-A server CPU aimed at AI and data-center workloads, with 144 cores, 256-bit SVE2 execution, 12 DDR5 channels, and up to two sockets per node. Its stacked chiplet design puts core dies on TSMC N2P while SRAM and I/O remain on N5, allowing advanced compute technology without putting the entire chip on the newest process. Fujitsu’s main efficiency lever is ultra-low voltage—reported as about 30% below comparable designs—alongside power-saving vector techniques and a floating-point register cache for high-locality workloads such as GEMM. It plans both a 500 W high-performance SKU and a 350 W efficient SKU, while a future Monaka-X is expected to add 1.4 nm fabrication and NVLink Fusion support.
Read the source →Stripe Paid $7.5 Billion For OpenRouter. You Are Living In The Age Of Startups.
The video interprets Stripe’s reported $7.5 billion purchase of OpenRouter as a major signal that demand for AI-model access is becoming economically central, rather than as a GPU or model-training bet. It contrasts the price with OpenRouter’s reported $1.3 billion valuation in May and points to weekly token volume that it says grew roughly 24,000-fold since August 2023, doubling every 11 weeks for three years. The presenter argues that Stripe’s own payments data led it to treat the AI “singularity” as having begun on January 1, and reads the premium as anticipation of further rapid growth. The conclusion is an explicitly bullish case for startups, incumbents, and careers exposed to AI adoption, though it is an interpretation rather than independently demonstrated causation.
Read the source →They Found a Way to Steal AI’s Reasoning
The video examines an alleged jailbreak that exposed reasoning traces AI labs had tried to keep hidden, arguing that the issue is broader than ordinary model distillation. It pushes back on portrayals of Chinese labs’ distillation work as inherently illicit, describing distillation as a common research technique that still requires useful training data. The presenter says the exploit had been patched before the associated paper was published, but treats its ability to extract hidden traces as evidence that reasoning protection can fail in unexpected ways. The video frames this as a security and competitive concern because detailed reasoning data could make replication or imitation more effective.
Read the source →Qwen 3.8 27B is a game changer.
A Reddit poster reports that their team found Qwen 3.8 27B comparable to GPT Luna for coding and claims its OCR output was better than Gemini 3.5 Flash Lite in an internal pipeline. The practical implication for the poster is cost: they say a move to owned hardware could pay back in under two months, making this the first local model their team considers more than a novelty. The post predicts that improving quantization and inference could make small local models increasingly competitive with hosted systems. These are anecdotal, unbenchmarked reports from one user, not an independently verified model evaluation.
Read the source →v2.1.243
Claude Code 2.1.243 adds observability and enterprise-control features, including a per-loop breakdown in /usage, curated and ordered model pickers, configurable main and subagent prompt-cache TTLs, and contracted-price support for cost reporting. It also adds Console-account sign-in without requiring an API key, clearer status information about settings precedence and GitHub/web setup, and visibility into each subagent’s model and effort level. The release fixes reliability problems across MCP reconnection, API retries, background subagent wakeups, cloud-session resume, plugin handling, hooks, and containerized cross-session messaging. It further reduces native Linux x64 download size from roughly 340 MB to 75 MB through zstd compression and reports 40–70 MB lower per-session resident memory through on-demand code loading.
Read the source →Lecture 113: Every Microsecond Matters: Achieving Near Speed-of-Light Latency in GPU Collectives
This lecture presents research on reducing GPU-collective latency toward the physical speed-of-light limit, focusing on cases where message sizes are small, collectives occur repeatedly, and communication sits on the application’s critical path. It distinguishes this latency-bound regime from large transfers, where bandwidth dominates and lower startup latency has less impact. The work was conducted in close collaboration with NVIDIA’s NCCL team and is framed around collective communication used in AI training and related workloads. Its central engineering premise is that seemingly tiny per-collective delays compound when synchronization happens many times in a critical computation.
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